1. Field of the Invention
Embodiments of the invention relate to a stacked semiconductor device and a method for fabricating the stacked semiconductor device. In particular, embodiments of the invention relate to a stacked semiconductor device including a single crystalline silicon structure and a method of fabricating the stacked semiconductor device.
This application claims priority to Korean Patent Application No. 2005-63997, filed on Jul. 15, 2005, the subject matter of which is hereby incorporated by reference in its entirety.
2. Description of Related Art
As the design rules for semiconductor devices decrease, the sizes of unit cells, conductive patterns, and intervals between the conductive patterns in semiconductor devices decrease accordingly. However, as the sizes of the conductive patterns and intervals become smaller, the electrical resistances of the conductive patterns may increase greatly. Additionally, the relatively small patterns are not readily formed through conventional semiconductor fabrication techniques, so it may not be possible to form patterns having the desired dimensions.
Thus, a method for fabricating a stacked semiconductor device has been developed in order to avoid the difficulties described above, which are caused by using conventional methods for fabricating semiconductor devices. In the stacked semiconductor device, unit elements such as metal oxide semiconductor (MOS) transistors are vertically stacked on a substrate. To manufacture the stacked semiconductor device, a thin film serving as a channel layer is formed on or over the substrate. The thin film generally has a crystalline structure that is substantially the same as the crystalline structure of a bulk silicon substrate. Thus, a single crystalline silicon layer is usually used as the channel layer in the stacked semiconductor device. The single crystalline silicon layer may be formed by thermally treating an amorphous silicon layer after the amorphous silicon layer has been formed on a seed layer containing single crystalline silicon. Alternatively, the single crystalline silicon layer may be formed through a damascene process. In the damascene process, after forming a trench exposing a seed, the single crystalline silicon layer may be formed in the trench through a selective epitaxial growth (SEG) process. When the single crystalline silicon layer is formed through the damascene process, the single crystalline silicon layer may have crystalline structure that is substantially superior to that of the single crystalline silicon layer formed through the thermal treatment process.
Figure (FIG.) 1 is a cross-sectional view illustrating a single crystalline silicon layer formed through a conventional damascene process. The single crystalline silicon layer may be used in a conventional stacked semiconductor device.
Referring to FIG. 1, a damaged portion 24 of a seed pattern 16 is generated while forming a trench 20 in order to form a single crystalline silicon layer 22 because an upper portion of the seed pattern 16 is exposed through the trench 20. When the seed pattern 16 includes the damaged portion 24, the single crystalline silicon layer 22 has a poor crystalline structure because the single crystalline silicon layer 22 is formed by an epitaxial process using the seed pattern 16.
A first insulating interlayer 12 and a second insulating interlayer 18 are somewhat excessively etched to form the trench 20 exposing the upper portion of the seed pattern 16 so that a bottom of the trench 20 is higher than a surface of the seed pattern 16, relative to a surface of the substrate 10. In the conventional stacked semiconductor device of FIG. 1, an etching gas for forming the trench 20 may not permeate into an interface between the insulating interlayer 12 and the seed pattern 16 because an upper portion of the seed pattern 16 is tapered away from the substrate 10. As a result, a silicon fence 26 is formed at the upper portion of the seed pattern 16.
Because the single crystalline silicon layer 22 does not grow properly from the silicon fence 26, a portion of the single crystalline silicon layer 22 formed on the silicon fence 26 may be thinner than other portions of the single crystalline silicon layer 22. When the single crystalline silicon layer 22 is used as a channel layer of the stacked semiconductor device, charge carriers may be less mobile at the portion of the single crystalline silicon layer 22 formed on the silicon fence 26 than at other portions. Thus, a response speed of a unit element formed on the single crystalline silicon layer 22 in the stacked semiconductor device may be reduced.
When a contact plug is formed through the portion of the single crystalline silicon layer 22 formed on the silicon fence 26, a contact area between the contact plug and the single crystalline silicon layer 22 may be relatively small and thereby increase a contact resistance of the stacked semiconductor device.
The single crystalline silicon layer 22 may not be properly grown from the silicon fence 26 of the seed pattern 16. Thus, the single crystalline silicon layer 22 may have an undesired crystalline structure and voids 28, which may occur in a central portion of the single crystalline silicon layer 22.
Therefore, a stacked semiconductor device including a single crystalline structure having a desirable crystalline structure without voids or crystalline defects is needed.